This invention relates generally to an integrated circuit. More particularly, the present invention relates to technique which can be applied effectively to an integrated circuit having regions in which a plurality each of input and output circuits can be formed in such a manner as to form pairs that correspond to a plurality of external connection pads, respectively, such as gate arrays.
Integrated circuits (which will also be called "ICs" hereafter) can be broadly classified into ICs having high versatility, such as standard logic semiconductor integrated circuits, and custom ICs, such as gate arrays, that are produced in accordance with customers' requirements. Being mass-produced, versatile ICs are economical but are not free from the problem that a large number of ICs are necessary in order to form circuits that are required by customers. The custom ICs are produced in order to solve this problem. Various contrivances are made to the custom ICs in order to satisfy customers' requirements. An example of such contrivances can be seen in ICs for gate arrays.
In a typical gate array, a large number of buffer portions are formed around an internal circuit which includes a large number of basic cells. The internal circuit includes a large number of basic cells in order to easily form a logic circuit required by a customer, and the desired logic circuit can be constituted within a short period by connecting these basic cells by aluminum wirings, whenever necessary. The buffer portions have an input circuit region and an output circuit region so that the input and output circuits can form pairs which correspond to a plurality of external connection pads, and that the arrangement of the input-output pins can be obtained easily as stipulated by the customer. When the corresponding external connection pads are input pins, only the input circuit region is used with the output circuit region being not used. When the corresponding external connection pads are output pins, on the contrary, only the output circuit region is used while the input circuit region is not used.
In other words, in accordance with ordinary methods, only an input circuit is connected between an external connection pad, to which an input signal is applied from outside, and an input terminal of an internal circuit when the input signal is applied to the pad. When an output signal is taken out from the external connection pad, on the other hand, only an output circuit which is formed so as to correspond this pad is connected between an output terminal of the internal circuit and this external connection pad.
The utilization ratio of an internal circuit portion has become extremely high as the scale of systems is ever-increasing. However, only a predetermined number of basic cells, which are contained in the internal circuit, are disposed on one main plane of a substrate. On the other hand, as to the buffer portion, the utilization ratio is low and many useless regions are contained as described above.
The present invention contemplates to improve the substrate utilization ratio of custom ICs such as gate arrays.